The disclosure relates to a method for fabricating a vertical channel transistor in a semiconductor device, and more particularly, to a method for forming a surrounding gate electrode of a vertical channel transistor in a semiconductor device.
As semiconductor devices become more highly integrated, the dimensions of the cells integrated on a wafer begin to decrease. This decrease in the cell dimensions can cause to a decrease in the channel length of a planar-type transistor, thus, a shorting effect, such as a Drain Induced Barrier Lowering (DIBL), a hot carrier effect or a punch-through effect, may occur.
The transistor in a giga-bit DRAM device requires at least an area of 4F2, where F is minimum feature size, thus, a reduction in cell dimensions and cell area upon integration will be unavoidable. Therefore, a means to maintain the transistor channel length while increasing the degree of integration in the DRAM device is necessary. In order to overcome the limitations on integrating planar-type transistors, conventional art suggests using vertical channel transistors.
FIG. 1 displays a cross-sectional view illustrating a conventional method for forming a vertical channel transistor in a semiconductor device.
As shown in FIG. 1, a substrate 100 is etched to a first predetermined depth Du using a hard mask pattern 120 as an etch barrier to form an upper pillar pattern 110A. A pad oxide layer 130 may be interposed between the hard mask pattern 120 and the upper pillar pattern 110A.
A spacer (not shown) is formed on the sidewalls of the upper pillar pattern 110A and the hard mask pattern 120, and a lower pillar pattern 110B is formed by etching the substrate 100 to a certain depth DL lower than the first predetermined depth DU using the hard mask pattern 120 and the spacer as etch barriers. Herein, the lower pillar pattern 110B and the upper pillar pattern 110A are connected to each other forming a single-body structure.
Isotropic etching of the substrate 100 is performed, forming the lower pillar pattern 110B with a recessed, predetermined width W1, narrower than the predetermined width of the upper pillar pattern W2. A gate insulation layer 140 is then deposited encapsulating the resultant pillar pattern structure. A surrounding gate electrode conduction layer is deposited surrounding the pillar patterns and the gate insulation layer 140, and spacer etching of the surrounding gate electrode conduction layer is performed to form the a surrounding gate electrode 150 surrounding the lower pillar pattern 110B.
As described above, a first width W1 of the lower pillar pattern 110B is smaller than and supports a second width W2 of the upper pillar pattern 110A, thus, forming an unstable structure. As a result, the pillar patterns 110 lean or collapse, restricting the possible degree of integration in accordance with the conventional method for forming the vertical channel transistor. Therefore, it is impossible to implement the conventional vertical channel transistor in semiconductor devices having narrow line widths of approximately 30 nm or less.
The hard mask pattern 120 on the pillar pattern 110 serves an etch barrier during several process steps of the fabrication, i.e. a pillar pattern formation process, a planarization process, and a damascene word line formation process. During the surrounding gate electrode formation process, a large portion of the hard mask pattern 120 may be damaged when etching the surrounding gate electrode conduction layer. Therefore, the hard mask pattern 120 cannot serve as a suitable etch barrier in subsequent processes, e.g., the damascene word line formation process, without exposing and putting at risk for damage the pillar patterns 110 located below the hard mask pattern 120.
In addition, at the etching process of the surrounding gate electrode conduction layer deposited encapsulating the sidewalls of the upper pillar pattern 110A, the gate insulation layer 140 formed on bottom of a gap region between the neighboring pillar patterns 110 can be exposed and damaged. Thus, the substrate 100 can also become damaged.
FIG. 2 displays a conventional vertical channel transistor under a Scanning Electron Microscope (SEM).
As shown in FIG. 2, since the lower pillar pattern has a smaller width than the upper pillar pattern, the pillar pattern can lean or collapse during the formation process of the vertical channel transistor. Therefore, when the vertical channel transistor is formed according to the conventional art, there is a limitation in improving the degree of integration in the semiconductor devices.